Partha De is PhD Candidate in the School of Computing and Information Systems at The University of Melbourne.
His research involves design of side channel attack resistant cryptographic ASIC systems. His work is supervised by Prof Udaya Parampalli (Unimelb) and Prof Chittaranjan Mandal (IIT Kharagpur).
Partha holds Bachelor of Technology degree in Computer Science and Engineering from West Bengal University of Technology (2005). He completed a Postgraduate Diploma in Information Technology (2007) and Masters in Computer Science and Engineering (2015) from IIT Kharagpur.
His publications include:
- Partha De, Kunal Banerjee, Chittaranjan Mandal, Debdeep Mukhopadhyay. Circuits and synthesis mechanism for hardware design to counter power analysis attacks. Euromicro Conference on Digital System Design (DSD), Verona, Italy, 2014, pages: 520–527. DOI: 10.1109/DSD.2014.61
- Partha De, Kunal Banerjee, Chittaranjan Mandal. A BDD based secure hardware design method to guard against power analysis attacks. International Symposium on VLSI Design and Test (VDAT), Coimbatore, India, 2014, pages: 1–2. DOI: 10.1109/ISVDAT.2014.6881088
- Partha De, Chittaranjan Mandal, Kunal Banerjee, “A BDD based circuit synthesis approach to counter power analysis attacks,” 27th IEEE International Conference on VLSI Design, Mumbai, India, 2014
- Partha De, Kunal Banerjee, Chittaranjan Mandal, Debdeep Mukhopadhyay. Designing DPA resistant circuits using BDD architecture and bottom pre-charge logic. Euromicro Conference on Digital System Design (DSD), Santander, Spain, 2013, pages: 641–644. DOI: 10.1109/DSD.2013.128